This invention relates to a high-speed serial interface, especially in a programmable logic device, which may operate at different data rates.
Recently, PLDs have begun to incorporate high-speed serial interfaces to accommodate high-speed (i.e., greater than 1 Gbps) serial I/O standards—e.g., the XAUI (10 Gbps Extended Attachment Unit Interface) standard. In accordance with the XAUI standard, a high-speed serial interface includes transceiver groups known as “quads,” each of which includes four transceivers and some central logic.
In one implementation, each transceiver is divided into a physical medium attachment (PMA) portion or module which communicates with outside devices, and a physical coding sublayer (PCS) portion or module which performs serial processing of data, for transmission to, or that is received from, those outside devices. Currently available PMA modules and PCS modules overlap in terms of the data rates that each will support, but the maximum data rate of available PMA modules exceeds the maximum data rate of available PCS modules. Therefore, up to a certain data rate, the PCS module of each channel can support the data rate of the PMA module of that channel. However, beyond that data rate, the currently available PCS module cannot support the data rate of the PMA module.
It would be desirable to be able to support the data rate of currently available PMA technology using currently available PCS technology. It would further be desirable to be able to do so efficiently in a programmable logic context.